Timing

Timing 201 #14: The Case of the Holdover Clock Phase Noise

Author: Kevin G. Smith

Introduction

Recently, one of my colleagues was asked by a customer about a particular jitter attenuator (JA) and its output clock phase noise performance when in holdover. After some discussion, I thought a few comparison phase noise plots would best illustrate typical holdover performance. This idea prompts this post’s topic, The Case of the Holdover Clock Phase Noise.

The “Bottom Line Up Front” answer is that a JA’s holdover output clock phase noise will generally look like that of a single loop PLL clock generator. This will be made clear in the plots to follow. For the purpose of this discussion, I will start with the Skyworks Si5395 which is a popular narrowband DSPLL jitter attenuator and use it as a vehicle to review holdover and free-run in general. I will then give some example phase noise plots for both the Si5395 and the Si5397 which supports 4 narrowband DSPLLs. These devices have different architectures but very similar holdover responses. Finally, I will close the article with a few comments regarding application considerations.

Holdover versus Free-run

In normal synchronous mode operation, a JA such as the Si5395 will be synchronized (locked) to a valid input clock. Here the term valid means the input clock is present and within frequency per the frequency plan, i.e. no LOS (Loss of Signal) or OOF (Out of Frequency) flags are asserted.

The Holdover (HO) and Free-run (FR) modes of operation are closely related in that the DSPLL is unlocked in both cases when there is no valid input clock. The distinction is that Holdover Mode, unlike Free-run mode, configures the output clock frequency based on an average of the input clock frequency prior to loss.

Below is an annotated and highlighted state diagram modified after Figure 2 in the Si5395/94/92 Reference Manual si5395-94-92-family.pdf that explains the transitions between states. The Reference Manual goes into more details. Note that, from a phase noise point-of-view, there is little difference between HO and FR except for the carrier frequency.

Si5395/94/92 Modes of Operation

Example Si5395 Dual-Loop Architecture

Consider the DSPLL Dual-Loop architecture in the figure below taken from Figure 2 in the White Paper Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks. This basic approach is used in our dual-loop jitter attenuators such as the Si5395/94/92, Si5386, and Si5345/44/42. The Outer Loop (OL) Digital Loop Filter modulates the Inner Loop (IL) feedback divider and the IL VCO output is f_OUT. In this architecture, the IL behaves as the “DCO” of the OL. As was discussed in previous blog posts, Timing 201 #7: The Case of the Dueling PLLs – Part 1, and Timing 201 #8: The Case of the Dueling PLLs – Part 2, the IL bandwidth must be much more wideband than the OL bandwidth. The Si5395 IL BW is fixed at ~ 1 MHz and the narrowband OL jitter attenuator bandwidths are selectable from 100 mHz to 4 kHz.

The main thing to recognize via this figure is that a wideband clock generator lies at the heart of the dual loop jitter attenuator. If f_IN is lost and holdover history is valid, then the modulation of the feedback divider is fixed to yield an output clock based on the prior average input clock frequency. On the other hand, if f_IN is lost and holdover history is invalid, then the feedback divider is simply configured to yield a nominal frequency output clock based on the frequency plan.

Other JAs, such as the multi-DSPLL Si5397, do not have the exact same architecture as the Si5395. However, there is still a wideband PLL that relies on a reference such as a crystal or XO to provide the HO clock. The HO behavior for both the Si5395 and Si5397 devices will be illustrated in the example phase noise plots below. DSPLL bandwidths of 100 Hz and 4 kHz will be applied in each case so we can clearly distinguish the locked and holdover modes.

Phase Noise Example (1) – Si5395 100 Hz BW HO vs. Locked

In the first example phase noise plot above, there is a data trace Tr1 for the Si5395 in holdover and a memory trace Tr2 for the Si5395 when locked with BW = 100 Hz. In this example and all others, the input clock is a moderately low phase noise 10 MHz 100 mVpp sinusoid from an AWG.

There are some notable features that are helpful when reviewing such phase noise plots. Recognizing these features can help you be a “phase noise plot whisperer” 😊.

The locked trace shows 2 “humps” where the phase noise markedly changes slope. There is a locked close-in offset frequency hump around 100 Hz and a far-out offset frequency hump around 1 MHz as expected.
Recall that a PLL’s phase noise is determined by low pass filtered contributions from the input reference clock path and detector noise (PFD+CP) plus high-pass filtered contributions from the VCO. These typically combine to create a relatively flat region or “plateau” in the phase noise prior to a jitter attenuation slope, e.g. 40 dB/dec for a Type II PLL. This characteristic distinguishes PLL phase noise from independent oscillator phase noise. (Here we see tilted rather than flat plateaus in the phase noise response.)
When the input clock is lost, and the Si5395 goes into HO, the ~100 Hz close-in hump disappears and the trace is reminiscent of a wideband (1 MHz bandwidth) clock generator’s phase noise output. The NB PLL is out of the picture. The Si5395 phase noise in holdover is very similar to that of its “cousin” device, the Si5391 clock generator in normal operation. See for example Figure 8.1 in si5391-datasheet.pdf.
Also, in HO, the close-in phase noise follows that of the reference, in this case an on-chip oscillator working with an external 48 MHz crystal.
The HO and Locked phase noise are the same once past the PLL noise, typically between 1 and 2 decades above the DSPLL bandwidth. In this case, the curves merge around 2 kHz offset

Phase Noise Example (2) – Si5395 4kHz BW HO vs. Locked

In the second example phase noise plot above, there is a data trace Tr1 for the Si5395 in HO and a memory trace Tr2 for the Si5395 when locked with BW = 4 kHz.

Notable features are as follows.

Again, the locked trace shows 2 “humps” where the phase noise markedly changes slope. This time the “close-in” offset frequency hump has moved out to somewhere around 4 kHz and the far-out offset frequency hump remains around 1 MHz as expected.
When the input clock is lost, and the Si5395 goes into HO, the ~4 kHz close-in hump disappears and the trace reverts to a wideband clock generator’s phase noise output.
The close-in HO phase noise again follows the 48 MHz crystal oscillator and looks the same as before.
The HO and Locked phase noise are the same once past the PLL noise, typically between 1 and 2 decades above the DSPLL bandwidth. In this case, the curves merge around 100 kHz offset.
The locked 12 kHz to 20 MHz phase jitter is higher when the BW = 4 kHz versus 100 Hz as expected since there is less jitter attenuation.

Phase Noise Example (3) - Si5397 100 Hz BW HO vs. Locked

The Si5395 only has 1 DSPLL that can be configured for a narrow bandwidth JA application. The Si5397 by contrast has a different architecture and supports 4 DSPLLs that can be independently configured for JA applications. The tradeoff to this flexibility is a reduced maximum output frequency and a little more phase jitter.

In this third example phase noise plot above, the Si5397 HO behavior appears similar to that of the Si5395.

The locked trace similarly shows 2 “humps” where the phase noise markedly changes slope. Again, the close-in offset frequency hump is somewhere around 100 Hz and the far-out offset frequency hump is around 1 MHz as expected.
When the input clock is lost, and the Si5397 goes into HO, the ~100 Hz close-in hump disappears and the trace is reminiscent of a wideband clock generator’s phase noise output.
The close-in HO phase noise follows that of the reference, in this case an internal 48 MHz crystal as this example Si5397 device is a Grade J.
The HO and Locked phase noise are the same once past the PLL noise, typically between 1 and 2 decades above the DSPLL bandwidth. In this case, the curves merge around 1 kHz offset.

Phase Noise Example (4) – Si5397 4 kHz BW HO vs. Locked

Finally, in this fourth and last example phase noise plot above, the Si5397 HO behavior is again similar to that of the Si5395.

The locked trace shows 2 “humps” where the phase noise markedly changes slope. The close-in offset frequency hump is somewhere around 4 kHz and the far-out offset frequency is around 1 MHz as expected.
When the input clock is lost, and the Si5397 goes into HO, the ~4 kHz close-in hump disappears and the trace is again reminiscent of a wideband clock generator’s phase noise output.
In HO, the close-in phase noise follows that of the internal 48 MHz crystal oscillator and looks identical to the earlier case.
The HO and Locked phase noise are the same once past the PLL noise, typically between 1 and 2 decades above the DSPLL bandwidth. In this case, the curves merge just past 100 kHz offset.

Some Applications Considerations

The behavior of these devices when in HO or FR suggests several items to keep in mind:

It is not necessarily true that the HO or FR case will have significantly less phase jitter vs. the locked case. For example a low jitter input clock and a narrow BW DSPLL can have similar phase jitter in both holdover and locked states. This is yet another reason to always monitor the LOS, OOF, and LOL flags.
As is frequently noted in our literature, the holdover reference (XTAL or XO) determines the output frequency stability and accuracy when the device is in HO or FR.
Finally, the fact that the JA can operate in FR as a clock generator can be useful for testing and if one simply wants to reduce the inventory of unique clock devices.

Summary

In all of these Si5395 and Si5397 examples, the phase noise response changed in holdover from a two PLL response to a one PLL response. Past 100 kHz, the phase noise plots did not change and the impact of the 1 MHz bandwidth reference loop was always visible.

I hope you enjoyed this Timing 201 article and that these comparison holdover plots were illustrative and useful.

As I write this post, we are approaching the 2025 Thanksgiving holiday here in the US. In recognition of this holiday, let me state that I am thankful for both this forum and for you the readers.

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@skyworksinc.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading.

Cheers,

Kevin

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By Kevin G. Smith Sr. Principal Applications Engineer

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