Timing

Timing 201 #13: The Case of the Speed-up Cap.

Timing 201 #13: The Case of the Speed-up Cap

Author: Kevin G. Smith

Introduction

It is always interesting when the addition of a single passive component can greatly improve circuit performance. This blog post discusses just such a situation.

Some oscillators, especially high stability performance TCXOs and OCXOs, may operate best at supply voltages higher than that of a particular receiving clock device input buffer. So for example, a single-ended 3.3 V LVCMOS TCXO output clock will need to be followed by a voltage divider when driving a 1.8 V LVCMOS input clock buffer.

Generally, we want the fastest input clock slew rate for the lowest jitter. However, the combination of a voltage divider plus load capacitance forms a low pass filter that slows down the input clock’s slew rate. The load capacitance is due to the receiving device’s input capacitance, trace capacitance, plus any other routing parasitic shunt capacitance.

Fortunately, we can add a “speed-up” capacitor in parallel to the first voltage dropping resistor to compensate for the load capacitance and make the resistive voltage divider look more ideal. See the image below modified after one from the Si5386 Rev. E Reference Manual. In this schematic, C1 is the speed-up cap.

We use the term “speed-up cap” loosely here as a nod to the fact that adding this capacitor speeds up the edge rate. It is really a compensation capacitor similar to how X10 oscilloscope probes are compensated. How to size this capacitor and how well it can work is the subject of this blog post, The Case of the Speed-up Cap.

How do we size the speed-up cap?

The basic approach is to match the time constants as when equalizing an oscilloscope probe. Per the figure above, ignore the 0.1 uF AC-coupling capacitors as transparent to this analysis. (Whether one DC-couples or AC-couples the input clock depends on the application.)

Let
Z1 = R1//C1 where “//” indicates the components are in parallel with each other
Z2 = R2//C2 where C2 represents the clock IC load capacitance

In this case voltage ratio k = 1.8 V / 3.3 V = 0.54545… => Z2 = (k/1-k)Z1 = 1.2*Z1 or 0.83*Z2 = Z1
Ideally, we want this relation to hold true for all frequencies.
Let 0.83*R2 = R1 so we can write

Multiply top and bottom by (1+sR2C2).

We want to match the time constants so that R1C1 = R2C2 and the factor in parentheses = 1.
Therefore, C1 = (R2/R1)*C2 = 1.2*C2.

In the example below, the load capacitor CL = C2 = 1.3 pF.
Therefore C1 = 1.2*1.3 pF = 1.56 pF. The closet practical value is 1.6 pF which is what we will use in the simulation example below.

Simulation Example Results

As a demonstration of how the speed-up cap can minimize slew rate degradation, I will be simulating several cases in HyperLynx. The goal is to voltage divide a 3.3 V clock down to 1.8 V and meet Si5363 jitter attenuator input clock slew rate requirements. Per the si5361-62-63-datasheet.pdf, LVCMOS (INx/INxb) Slew rate SR = min 0.2 or typ 0.4 V/ns. The main points of the simulations are listed below.

The Si544 I2C programmable oscillator will source a 19.44 MHz 3.3 V LVCMOS single-ended clock, simulated with IBIS file si544.ibs. (Note that you can actually operate the Si544 at 1.8 V but here it stands in for oscillators such as TCXOs and OCXOs that may operate best at 3.3 V.)
We will use a large resistor value voltage divider where Rseries = 15 kΩ, Rshunt = 18 kΩ.
1. These resistor values are sized to minimize current draw.
  
  For other candidate resistor values, you may wish to use a practical resource such as Damien Douxchamps’ Voltage divider calculator for real E-series resistors
2. DC current through the voltage divider =3.3/(15E3 + 18E3) = 0.0001 A or 0.1 mA or 100 mA.
3. 3.3 V *18E3/(15E3+18E3) = 1.8 V.
Load capacitor CL = 1.3 pF.

This is a standard capacitor value and also just a bit larger than the typical Si5363 jitter attenuator 1.25 pF input capacitance. See si5361-62-63-datasheet.pdf LVCMOS (INx/INxb) Capacitance C_{IN_SE}.

Attached is a relatively simple HyperLynx schematic, Timing_201_13_Speed-up_Cap_Sim_Schematic.ffs. See the screen capture below. R1 and R2 constitute the Rseries and Rshunt resistive voltage divider components. U1 is the Si544 I2C programmable oscillator sourcing the LVCMOS clock. R3 is the Near End Termination or series matching resistor necessary when driving into a tranmission line load. C1 is the speed-up capacitor and C2 is the load capacitor otherwise referred to as CL. TL1 is a simple 50 Ω lossless transmission line with adjustable delay.

This simulation schematic can be used to simulate several important cases by changing values as listed in the table below.

Also attached are the simulation results for each of the cases in Timing_201_13_Speed-up_Cap_Sims.xlsx. The results can best be understood by looking at the plots in worksheet “Plots” and reproduced below. There is also a “Zoom Plots” worksheet that looks at the rising edges where you can see the transmission line delay. Cases 1, 3, and 4 have roughly similar edge responses versus the red Case 2 trace where the capacitive load “shark fins” the waveform.

Application Considerations

Here are some general application considerations when implementing resistive voltage dividers as discussed.

Minimize the load capacitance.

A TCXO might be specified into a 15 pF load but is that really required or is it a maximum? In most applications, a voltage divider simply won’t work together with such a high load capacitance and yield a decent edge rate. In such a case, a speed up cap is mandatory.
Size the resistors, trading off accuracy versus DC loading.
1. What is the maximum resistive load the oscillator can drive? If this is not specified, something on the order of kΩ should be a good starting value to validate.
2. An optional DC block capacitor from Rshunt to GND will allow one to use lower value resistors.
3. Large value resistors are best where the oscillator has significant internal source impedance and/or if a series matching resistor is present as in the simulations discussed above. Note that if you simulate assuming an ideal source only, you may miss the fact that the output won’t quite reach nominal VOH.
4. Smaller resistor values can be used to trade-off more current draw for less filtering impact. For example, if we reduce Rseries = 1.5 kΩ and Rshunt = 1.8 kΩ, then the DC current through the voltage divider increases to3.3/(1.5E3 + 1.8E3) = 0.001 A or 1 mA

Summary

The bottom line is that adding a speed-up cap to your clock voltage dividers can minimize slew rate degradation and improve jitter performance. So keep this idea in your “bag of tricks”. Even if you think you won’t need it, consider leaving an optional footprint for it on your PCB just in case.

I hope you have enjoyed this Timing 201 article.

As always, if you have topic suggestions or questions appropriate for this blog, please send them to kevin.smith@skyworksinc.com with the words Timing 201 in the subject line. I will give them consideration and see if I can fit them in. Thanks for reading.

Cheers,

Kevin

Timing

By Kevin G. Smith Sr. Principal Applications Engineer

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