Skyworks family of JESD204B/C wireless jitter attenuators leverage our wireless DSPLL® TECHNOLOGY which offers unparalleled CMOS integration, reduced power, low noise and size without compromising the stringent performance and reliability required in wireless applications.
These solutions can meet the demanding performance requirements of enhanced Common Public Radio Interface (eCPRI) and CPRI applications for macrocells, small cells, remote radio heads (RRH), distributed antenna systems (DAS) and O-RAN applications.
Si5510 and Si5508 wireless jitter attenuators leverages our 5th generation wireless DSPLL® TECHNOLOGY targeting 5G applications and can generate low phase noise wireless clocks with less than 47 fs typical phase jitter. The Si5510 included a single DSPLL with two MultiSynths while the Si5508 supports just a single DSPLL.
Si538x wireless jitter attenuators leverages our fourth generation wireless DSPLL® TECHNOLOGY which can generate both wireless clocks with less than 100 fs typical phase jitter and low jitter general purpose clocks.