Loop Bandwidth Max (MHz)—
Input Frequency Min (MHz)48
Package TypeQFN64
ControlI2C/SPI
OPNSi5391P-A-GM
Line Impedance Match0
Clock Generatorstrue
Jitter Attenuating Clocksfalse
Number of Outputs12
Input Frequency Max (MHz)48
Intel x86 Clocksfalse
Package Size (mm)9x9
Real Time Clockfalse
Description12-Output Any-Freq Clock Gen
Frequency ReferenceExternal
4G/LTE Wireless Clocksfalse
56G SerDestrue
VDDO (V)1.8/2.5/3.3
Ouput Format(s)CML; HCSL; LVCMOS; LVDS; LVPECL
VDD (V)1.8; 2.5; 3.3
Jitter Recommended Range (fs)<
PCI Expressfalse
Phase Jitter (ps RMS)0.069
Spread Spectrumfalse
Synchronous Ethernet/1588false
DSPLLs0
Xtal Input Frequency48
Reference Inputs1
Output Format CategoriesDifferential; Single-Ended
PCIe PerformanceGen1/2/3/4/5
Standards Compliance—
Output Frequency Min (MHz)25
Embedded Xtaltrue
Loop Bandwidth Min (MHz)—
Output Frequency Max (MHz)625